This invention relates to a multi-chip module structure for use in general electronic appliances, and more particularly to a multi-chip module structure of the type suitably applied to a ceramic wiring board having a grid array of pins adapted to carry or support a plurality of semiconductor chips.
For example, "ICCD, '83 The New IBM 4831" is known as a prior art reference disclosing a multi-chip module structure. In this prior art multi-chip module structure, the number of power supply input/output (I/O) pins (inclusive of grounding pins) is different for a plurality of divisional board areas which are defined by dividing the board in accordance with individual semiconductor devices such as semiconductor chips or LSI's carried or supported by the module structure and ranges from zero to eleven. In other words, the number of power supply I/O pins differs from one location to another on the board at which individual semiconductor devices are supported by the module. Consequently, the amount of DC power supply voltage drop occurring between power supply I/O pins and each semiconductor device connected thereto differs with locations at which these semiconductor devices are supported, causing a decrease in the noise margin.
JP-A-61-27667 discloses another prior art wherein the pitch or distance between adjacent connecting pads arrayed on a board in the form of a grid (hereinafter simply referred to as the grid pitch of connecting pads) is made constant even when the grid pitch of pins of one semiconductor device carried on the board top surface is different from that of pins of another semiconductor device. This literature, however, fails to consider the positional relation between the connecting pads on the board top surface and I/O pins on the board bottom surface. Accordingly, even in this literature, the position of power supply I/O pins differs with respective divisional board areas allotted to individual semiconductor devices carried on the board.
It should therefore be understood that in any of the prior art the wiring for the power supply I/O pins of the ceramic multi-layer wiring board differs with the individual semiconductor devices and a power supply layer (including a grounding layer) can not be realized with a metallized pattern which has a constant configuration for all of semiconductor devices of the same type. This disadvantage seriously bottlenecks the design work for multi-chip modules carried out through the use of the Computer Aided Design (CAD) method.
In other words, the wiring for the power supply I/O pins of the ceramic multi-layer wiring board can not be prepared by sufficiently taking advantage of repeating an identical metallized pattern which is applied to individual semiconductor devices of the same type but is formed differently even for the identical type semiconductor devices.
Accordingly, the prior art fails to consider that the number of power supply I/O pins of the ceramic multi-layer wiring board supporting a great number of semiconductor devices and the number of through holes bridging the board should respectively be made identical for individual semiconductor devices of the same type and that the relative position of the power supply I/O pins to semiconductor device connecting pads should also be made identical for the individual identical type semiconductor devices, thus raising the following problems.
More particularly, in the prior art, an expansion layer, a power supply layer and a conversion layer which constitute a ceramic multi-layer wiring board and which are used in common for each semiconductor device of the same type differ with locations of the divisional board areas for individual semiconductor devices of the same type and have no repeat of pattern. Therefore, the design work and the mask preparation work for the commonly used layers become time-consuming and efficient check and inspection during the fabrication process of the ceramic multi-layer wiring board is difficult to achieve. Further, examination and detection of faults during the work for correcting manufacture defects and design defects is also time-consuming. In the previous explanation, the expansion layer is a layer adapted to transfer the grid pitch of semiconductor device connecting pads to the grid pitch of signal conductors of a signal wiring layer when both the grid pitches are inconsistent, and the conversion layer is a layer adapted to reduce the grid pitch of I/O pin connecting pads to the grid pitch of signal conductors of the signal wiring layer so that the former grid pitches are transferred to the latter grid pitch.